A CMOS 0.8mm FULLY DIFFERENTIAL CURRENT MODE BUFFER FOR HF SI CIRCUITS

This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reported without the explicit permission of the copyright holder. We present a high-frequency fully-differential current-mode buffer to interface off-chip currents with no significant degradation of the frequency response, and to measure current-mode ICs using standard equipment. This unit has been incorporated to the front end of a Switched-Current BandPass Σ∆ modulator which can in its turn be used to interface bandpass signals from on-chip current-mode sensors, and to interface RF signals for telemetry applications. Introduction: Current-mode circuits may be advantageous for applications involving sensors whose outputs are currents such as light and radiation sensors, some temperature and magnetic sensors, and many others found in biomedicine [1]. For these cases, processing directly in the current domain avoids using current-to-voltage converters and may hence yield faster operation than voltage-mode circuits. However, the speed advantages are only realized at fully if the input currents are generated on-chip. Otherwise, the circuit dynamics may become severely degraded due to parasitic time constants at the chip pads. This letter presents a CMOS current buffer to interface single-ended off-chip currents into on-chip fully-differential current-mode circuitry and include experimental results showing its performance as a stand-alone unit and as part of a CMOS 0.8µm BandPass Σ∆ SI modulator [2]. Illustrating the Speed Degradation in SI Interfaces: Consider the SI second-generation memory cell of Fig. 1(a). We have implicitly assumed that this memory is on-chip and that the capacitance of the driving stage is negligible as compared to the gate-to-source capacitance of the memory transistor C gs-bear in mind that mismatch considerations force using large channel area transistors. During phase φ 1 (sampling phase) this capacitance is charged with a time constant C gs /g m. Assume now that the memory cell is placed at the chip front-end, and we use the simplest possible interface: an off-chip linear resistor with resistance much larger than 1/g m (see Fig. 1(b)). Consequently the time constant changes from C gs /g m to (C gs + C pad)/g m. Because the pad equivalent capacitance C pad is typically large as compared to the inner capacitance, the high-frequency behavior …